FIG. 1 illustrates a cross sectional view of a semiconductor device based on Package-on-Package (PoP) technology. As shown in FIG. 1, a first semiconductor chip 20 is flip-chip mounted on a bonding pad 24 with a bump 22 made of a conductive material. The bonding pad 24 is formed on a first substrate 10 that is a wiring substrate made of glass epoxy. The first semiconductor chip 20 is fixed to the first substrate 10 with an under fill 25 that is made of an epoxy-based thermosetting resin or an epoxy resin in which an anisotropic conductive particle (e.g., an anisotropic conductive film or an anisotropic conductive paste) is dispersed. A land electrode 26 is electrically coupled to a second substrate 30 with a solder ball 32. A land electrode 14 is electrically coupled to the bonding pad 24 and to the land electrode 26 with a connection portion 18. A solder resist 28 and a solder resist 16 on both sides of the first substrate 10 prevent the solder from attaching to the surface of the first substrate 10 when solder balls 12 are formed.
The second substrate 30 is a wiring substrate. A land electrode 34 is formed on a face of the second substrate 30 toward the first semiconductor chip 20. The second substrate 30 is electrically coupled to the first substrate 10 with the solder ball 32. A solder resist 35 prevents the solder ball 32 from attaching to a surface of the second substrate 30. A second semiconductor chip 40 is stacked on the second substrate 30 using a die attach 45. A third semiconductor chip 50 is stacked above the second semiconductor chip 40 using a die attach 55. A bonding pad 36 is also on the second substrate 30 and is electrically coupled to the second semiconductor chip 40 and the third semiconductor chip 50 with a wire 42 and a wire 52, respectively. The bonding pad 36 is electrically coupled to the land electrode 34 with a connection portion 38. The second semiconductor chip 40 and the third semiconductor chip 50 are sealed with a sealing resin portion 60.
With the structure, the first semiconductor chip 20 is electrically coupled to the solder ball 12 via the bump 22, the bonding pad 24, the connection portion 18 and the land electrode 14. On the other hand, the second semiconductor chip 40 and the third semiconductor chip 50 are electrically coupled to the solder ball 12 via the wires 42 and 52, the bonding pad 36, the connection portion 38, the land electrode 34, the solder ball 32, the land electrode 26, the connection portion 18 and the land electrode 14.
Japanese Patent Application Publication No. 2002-110902 discloses semiconductor chips flip-chip mounted and stacked on a wiring substrate and a metal substrate available on each back face of the semiconductor chips. Japanese Patent Application Publication No. 2000-12765 discloses stacked modules on a motherboard where the modules have a semiconductor chip flip-chip mounted on the substrate. Additionally, the reference discloses a via for heat radiation formed in the motherboard and the module substrate.
However, it may be difficult to dissipate the heat generated by the semiconductor chip at the bottom of a semiconductor device based on a stacked chip configuration. Especially, if the semiconductor chip at the bottom is flip-chip mounted and/or if the substrate on the back side of the flip-chip mounted semiconductor chip is metal, the heat generated by the semiconductor chip may not be satisfactorily dissipated as most of the heats absorbed by the metal substrate, thus causing one or more problems in various components of the semiconductor device.